This invention relates generally to the simulation of electronic circuits, and more particularly to the simulation of such circuits at a switch level.
Digital MOS circuits, including high-speed full-custom chips, can consist of a few hundred thousand transistors. In fact, circuits of this size are now commonplace with the advent of Very Large Scale Integration (VLSI). After these circuits are designed, they are modeled (i.e., simulated) before being fabricated in silicon. This is because silicon fabrication is costly and time-consuming, and because simulation allows the operation of the circuits to be tested and analyzed relatively easily and inexpensively before fabrication.
Digital MOS circuits can be simulated at various levels of detail depending upon the amount of precision of the information required. For example, transistor-level simulation, which is very detailed, greatly increases the probability of the circuit working correctly when it is first fabricated in silicon. In addition, errors in layout, design, and timing that may be impossible to detect by other methods can be detected by a transistor-level simulation of the complete circuit.
The more detailed the level, however, the smaller the circuit that can be simulated in any reasonable amount of time. Transistor-level simulation is so slow and difficult to use that is not appropriate for very large circuits.
Simulations of large digital MOS circuits are usually performed with either gate-level modeling or switch-level modeling. Gate-level modeling, which involves building circuits from predetermined logic gate models, can validate the logic behavior of certain circuits, such as those designed in a standard-cell system that have validated gate-level models. For full custom circuits, however, gate-level modeling is inadequate because it does not properly simulate certain MOS circuit phenomena, such as bidirectional signal flow, resistance-ratio effects, and charge-sharing.
Switch-level modeling, which is exemplified in FIG. 1, addresses the drawbacks of gate-level modeling and transistor-level modeling. In switch-level modeling, each transistor 100 is replaced by a switch 110 having a conduction path 120 with a given resistance value represented as element 125. Depending upon the signal at a gate 130, switch 110 is either closed or opened thereby placing conduction path 120 into or out of the remaining circuit.
Switch-level modeling is not only relatively fast, it is more accurate than gate-level modeling because gate-level modeling uses specific input/output relationships which may not fit each circuit accurately. The speed and accuracy of switch-level modeling are two reasons that it is commonly used to simulate very large circuits, such as those with more than one hundred thousand transistors.
Most switch-level simulators, however, provide detail only at the logic simulation or state level and do not provide any timing information. Such pure logic simulation gives information about the logic-levels of signals without regard to the actual timing (i.e. delays) associated with signal changes.
Timing simulation is useful and sometimes necessary to obtain details about the signal waveform and information about when and how fast signals change. Some switch-level simulators provide details about the timing delays associated with signal changes. This is done, as shown by FIG. 2, by treating each node 200 of a circuit as a node 210 with an associated capacitance value 215 to ground.
Some conventional switch-level simulators model transistor conductances and node capacitances by "strengths," either from a discrete or a continuous set. "Strengths" are approximations of transistor conductances. Certain switch-level simulators provide timing by using these "strengths" as a measure of the node conductances from which delays are computed. Strengths and the delays calculated from strengths are only crude approximations of actual node conductance and circuit delay, however. The inaccuracy of these approximations is the principal source of timing inaccuracy by such conventional switch level simulators and the principal reason why most switch-level simulators are unable to resolve the output of a circuit correctly if dynamic logic is present.
The inability of conventional switch-level simulators to resolve the output of a circuit correctly will be illustrated by the exclusive OR circuit 300 shown in FIG. 3. Circuit 300 includes three drivers 310, 320, and 330. Driver 310, which is composed of transistors 315 and 317, receives an A input inverted. Driver 320, which is composed of transistors 325 and 327, receives a B input inverted. Driver 330, which is composed of transistors 335 and 337, is connected to the output of driver 320. Circuit 300 also includes exclusive OR gate 340, which is composed of transistors 342, 344, 346, and 348.
Conventional switch-level simulators which rely on strength propagation to determine the logic-levels in the circuit operate by propagating strengths across transistor channels. Thus, a node is assigned a strength equal to the smaller of the strength of the transistor and the strength of the node connected by the transistor. For such a mechanism to produce the correct result for circuit 300, the strengths of the six transistors 315, 317, 325, 327, 335 and 337 in the drivers 310, 320 and 330 have to be larger than the strengths of the four transistors 342, 344, 346 and 348 in exclusive OR gate 340. In actual design, this is usually not true. Therefore, this type of conventional switch-level simulator will not be able to simulate such a circuit correctly.
Another attempt to improve the accuracy of simulators has been the development of techniques for computing delay in certain circuits. Efficient algorithms to compute delay have previously been developed only for tree RC-networks. In tree RC-networks, there are no loops. Such algorithms can therefore not be used for the majority of circuits because most circuits do have loops.
Recently, two different techniques have been developed for determining delay in general RC-networks One technique is relaxation-based and appears to have a computation complexity of O(n.sup.3). The other technique has a computation complexity of O(n.sup.3) for planar networks and O(n.sup.6) for general networks this complexity is disadvantageous.
It would therefore be desirable to provide a system for switch-level modeling which generates accurate timing information.
Another desirable feature would be to provide such a system without large computation complexity.
It would also be desirable to provide a simulation system which executes rapidly.